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Espressif Systems /ESP32-H2 /SPI0 /SPI_MEM_INT_ENA

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Interpret as SPI_MEM_INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_SLV_ST_END_INT_ENA)SPI_MEM_SLV_ST_END_INT_ENA 0 (SPI_MEM_MST_ST_END_INT_ENA)SPI_MEM_MST_ST_END_INT_ENA 0 (SPI_MEM_ECC_ERR_INT_ENA)SPI_MEM_ECC_ERR_INT_ENA 0 (SPI_MEM_PMS_REJECT_INT_ENA)SPI_MEM_PMS_REJECT_INT_ENA 0 (SPI_MEM_AXI_RADDR_ERR_INT_ENA)SPI_MEM_AXI_RADDR_ERR_INT_ENA 0 (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA)SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA 0 (SPI_MEM_AXI_WADDR_ERR_INT__ENA)SPI_MEM_AXI_WADDR_ERR_INT__ENA

Description

SPI0 interrupt enable register

Fields

SPI_MEM_SLV_ST_END_INT_ENA

The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
SPI_MEM_MST_ST_END_INT_ENA

The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
SPI_MEM_ECC_ERR_INT_ENA

The enable bit for SPI_MEM_ECC_ERR_INT interrupt.
SPI_MEM_PMS_REJECT_INT_ENA

The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.
SPI_MEM_AXI_RADDR_ERR_INT_ENA

The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.
SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA

The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.
SPI_MEM_AXI_WADDR_ERR_INT__ENA

The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data